OPERATION

This device is a fully integrated power solution in a QFN-59 (10mmx12mmx4mm) package. For higher current applications, this device can be connected in parallel to provide a higher output current. This device employs constant-on-time (COT) control to provide fast transient response. The internal ramp compensation guarantees stable operation for applications using zero-ESR ceramic output capacitors.

RAMP Compensation

This device guarantees stable operation with zero-ESR ceramic output capacitors by using internal ramp compensation. A triangular RAMP signal is generated internally and superimposed onto the FB signal. The triangular RAMP signal starts to rise once RAMP + FB drops below the REF signal, and a SET pulse is generated. The RAMP signal’s rise time is fixed. The amplitude of the ramp compensation is selectable through the PMBus command D0h[3:1] to support wide operation configurations.

There is a tradeoff between the stability and load transient response. A larger RAMP signal provides higher stability but a slower load transient response, and vice versa. Consequently, it is necessary to optimize the ramp compensation selection based on the design criteria for each application.

APPLICATION INFORMATION

Operation Mode Selection

This device provides both forced CCM and pulse skip operations in light-load conditions.

Output Voltage Setting

A feedback resistor divider is required to set the proper feedback gain. The values of the feedback resistors are determined using Equation (1):

Where V₀ is the output voltage.

The output voltage feedback gain is determined with Equation (2):

To optimize the load transient response, a feed-forward capacitor (C_FF) must be placed in parallel with R1. Table 1 lists the values of the feedback resistors and the feed-forward capacitor for common output voltages.

This device offers output voltage programmability through the PMBus. In addition, the output voltage can be adjusted within a certain range through the PMBus by adjusting the internal reference voltage of the PWM controller (V_REF). The reference voltage, which has a default value of 0.6V, can be adjusted between 0.5V and 0.672V. For a given feedback resistor network, the upper and lower limits of the output voltage are determined with Equation (3) and Equation (4), respectively:

Two steps must be followed to program the output voltage through the PMBus:
1. Write the G_FB value determined by Equation (2) to register VOUT_SCALE_LOOP (29h).
2. Write the output voltage command to register VOUT_COMMAND (21h).

V_REF is updated automatically based on the output voltage command and G_FB.

Output voltage monitoring through the PMBus is enabled by setting the register VOUT_SCALE_LOOP (29h) with a value that matches the G_FB value calculated with Equation (2).

For applications where a PMBus interface is not required, V_REF = 0.6V is used by default, and operates in analog mode. The feedback resistors should be determined based on Equation (1).

Soft Start

The soft-start (SS) time can be programmed through the PMBus.

Pre-Bias Start-Up

The device is designed for monotonic start-up into pre-biased loads. If the output voltage is pre-biased to a certain voltage during start-up, both the high-side and low-side switches are disabled until the internal reference voltage exceeds the sensed output voltage at the FB pin.

Output Voltage Discharge

The output voltage discharge mode is enabled when the device is disabled through the CTRL pin. In this case, both the high-side and low-side switches are latched off. A discharge FET connected between SW and GND turns on to discharge the output capacitor. A typical on resistance for the discharge FET is about 60Ω. Once the FB voltage drops below 10% of the reference output voltage, the discharge FET turns off.

This feature can be enabled or disabled through the MFR_CTRL_VOUT (D1h) command.

Current Sense and Over-Current Protection (OCP)

This device features on-die current sense and a programmable positive current limit threshold. The device provides both inductor valley current limits (set by register D7h).

Inductor Valley Over-Current Protection (D7h)

During the LS-FET on state, the inductor current is sensed and monitored cycle by cycle. The HS-FET is only allowed to turn on if no over-current (OC) is detected during the LS-FET on state. If 31 consecutive cycles of an OC condition are detected, OCP is triggered.

During an over-current condition or output short circuit condition, if the output voltage drops below the under-voltage protection (UVP) threshold, the device enters OCP immediately.

Once OCP is triggered, the device either enters hiccup mode or latch-off mode, depending on the register. VCC or CTRL must be power recycled to re-enable the device once it latches off.

The inductor valley over-current limit can be programmed through register D7h, which sets the per-phase inductor valley current limit for both single-phase and multi-phase operation.

Negative Inductor Current Limit

When the LS-FET detects a negative current below the limit set through register D5h[2], the part turns off its LS-FET for a period of time to limit the negative current. The period is set through register D5h[3].

Under-Voltage Protection (UVP)

The device monitors the output voltage through the FB pin to detect an under-voltage condition. If the FB voltage drops below the UVP threshold (set through register VOUT_UV_FAULT_LIMIT), the UVP is triggered. After UVP is triggered, the device enters either hiccup mode or latch-off mode, depending on the PMBus selection. V_CC or CTRL must be power recycled to re-enable the device once it latches off.

Over-Voltage Protection (OVP)

The device monitors the output voltage using the FB pin connected to the tap of a resistor divider to detect an over-voltage condition. See the register VOUT_OV_FAULT_RESPONSE section on page 31 for additional information on OVP.

Output Sinking Mode (OSM)

The device enters OSM when the output voltage is more than 5% above the reference and below the OVP threshold. Once OSM is triggered, the device runs in forced CCM. The device exits OSM when the HS-FET turns back on.

Over-Temperature Protection (OTP)

The device monitors the junction temperature. If the junction temperature exceeds the threshold value (set by register OT_FAULT_LIMIT), the converter enters either hiccup mode or latch-off mode, depending on the PMBus selection. V_CC or CTRL must be power recycled to re-enable the device once it latches off.

Power Good (PG)

The device has an open-drain power good (PG) output. The PG pin can be configured as output-only or as an input and output pin by bit[0] of register MRF_CTRL_COMP (D0h).

For single-phase configuration, the PG pin should be configured as output-only.

For multi-phase operation, the PG pin should be configured as an input and output pin to detect faults from the slave phases. The PG pin must be pulled high to V¬¬CC or a voltage source with less than 3.6V through a pull-up resistor (typically 100kΩ).

PG is pulled low initially once input voltage is applied to the device. After the FB voltage reaches the threshold set by register POWER_GOOD_ON, the PG pin is pulled high after a delay set by register MFR_CTRL_VOUT.

PG latches low if any fault occurs, and the relevant protection feature is triggered (e.g. UV, OV, OT, UVLO, etc.). After PG latches low, it cannot be pulled high again until a new soft start is initialized.

If the input supply fails to power the device, PG latches low. Figure 4 shows the relationship between the PG voltage and the pull-up current.

Figure 4: Power Good Current vs. Power Good Voltage

Input Capacitor

The step-down converter has a discontinuous input current, and requires a capacitor to supply the AC current to the device while maintaining the DC input voltage. Use ceramic capacitors for the best performance. During layout, place the input capacitors as close to the IN pin as possible.

The capacitance can vary significantly with temperature. Capacitors with X5R and X7R ceramic dielectrics are recommended because they are fairly stable over a wide temperature range.

The capacitors must also have a ripple current rating that exceeds the converter’s maximum input ripple current. Estimate the input ripple current using Equation (5):

The worst-case condition occurs at VIN = 2VOUT, calculated with Equation (6):

For simplification, choose an input capacitor with an RMS current rating that exceeds half the maximum load current.

The input capacitance value determines the converter input voltage ripple. Select a capacitor value that meets any input voltage ripple requirements.

Estimate the input voltage ripple using Equation (7):

The worst-case condition occurs at VIN = 2VOUT, calculated with Equation (8):

Output Capacitor

The output capacitor maintains the DC output voltage. Use ceramic capacitors or POSCAPs. Estimate the output voltage ripple using Equation (9):

Where the module’s internal inductor is 0.36µH.

When using ceramic capacitors, the capacitance dominates the impedance at the switching frequency. The capacitance also dominates the output voltage ripple. For simplification, estimate the output voltage ripple using Equation (10):

The ESR dominates the switching-frequency impedance for POSCAPs, so the output voltage ripple is determined by the ESR value.

For simplification, the output ripple can be estimated using Equation (11):

PCB Layout Guidelines

Efficient PCB layout is critical achieve stable operation. For optimal performance, refer to Figure 5 and follow the guidelines below:

• 1. Place the input ceramic capacitors as close to the VIN and PGND pins as possible on the same layer of the device.
• 2. Maximize the VIN and PGND copper plane to minimize parasitic impedance.
• 3. Place the VIN vias at least 1cm from the part to minimize noise coupling from the input pulsating current.
• 4. Connect AGND to a solid ground plane through a single point.
• 5. Place sufficient output GND vias close to the GND pins to minimize both parasitic impedance and thermal resistance.
• 6. Keep the ISUM trace as short as possible. The ISUM trace should be away from the VIN copper in a multi-phase configuration. Vias should be avoided whenever possible.
• 7. Ensure that keep-out area is kept clean.
• 8. Avoid placing signal traces directly beneath the SW pad unless a PGND layer is used to provide shielding.

Figure 5: Recommended PCB Layout – Top Layer